A Successive Approximation (SAR) Analog to Digital Converter (ADC) has a relatively low conversion speed, but is well known as a low-power ADC because the SAR ADC does not include a static power consuming circuit.
The operational principle of a SAR ADC using charge redistribution will be described with reference to FIGS. 1 and 2. FIG. 1 is a circuit diagram of a SAR ADC in a sample mode, and FIG. 2 is a circuit diagram of the SAR ADC in a mode for a decision of the Most Significant Bit (MSB).
Referring to in FIGS. 1 and 2, a 4-bit ADC includes an array of capacitors C4, C3 and C2 for sample/hold and digital/analog conversion functions, and further includes a termination capacitor C1 to divide a reference voltage VREF with a step size of ½N, where N is the ADC resolution. Further, the 4-bit ADC includes a comparator CP to compare a sampled input voltage with a D/A conversion result, to thereby produce a 4-bit code B4 B3 B2 B1.
In a sample mode shown in FIG. 1, the lower terminals of all the capacitors, C1 to C4, are connected to a terminal of an input signal Vin, and the upper terminals are connected to a mid reference voltage VCM (=VREF/2).
In a mode for the Most Significant Bit (MSB) decision shown in FIG. 2, the lower terminals of all the capacitors C1 to C4 are connected to the mid reference voltage VCM and the upper terminals are floated. Then, the voltage difference VREF−Vin appears at the inverting (−) input terminal Vxn of the comparator CP. In this case, because the voltage at the non-inverting (+) input terminal Vxp is fixed to the reference voltage VCM, the voltage difference Δ(Vxp−Vxn) between both terminals of the comparator CP becomes Vin−VREF/2. Therefore, an MSB capacitor which should be 8C required in typical ADC designs can be removed. That is, the number of capacitors required for a 4-bit ADC design becomes 3 capacitors of C4 to C2.
If the polarity of the voltage difference Δ(Vxp−Vxn) (=Vin−VREF/2) is positive, it means that the voltage of the input signal Vin is greater than VREF/2, half of the input full scale. Thus, the MSB, B4, is decided to be 1, and the capacitor C4 is connected to the reference voltage VREF. In contrast, in the case where the polarity of the voltage difference Δ(Vxp−Vxn) is negative, the MSB is determined to be 0, and the capacitor C4 is connected to the ground GND.
After the C4-to-VREF or C4-to-GND connection, a settling time for DAC level at Vxn is given. Then, the comparator CP compares the node voltages of Vxp and Vxn, and a bit B3 is determined and, thereafter, the capacitor C3 is connected to either the reference VREF or GND depending on the bit B3 decision.
A A/D conversion for the sampled input signal is completed by repeating the above procedure until the Least Significant Bit (LSB) B1 is obtained. This code decision process is called successive approximation algorithm.
The DAC operation and the voltage difference Δ(Vxp−Vxn) at the input of the comparator CP is the core factor for the digital code decision in the SAR ADC, and it is represented by the following Eq. 1.
                                          Δ            ⁡                          [              i              ]                                =                                    V                              i                ⁢                                                                  ⁢                n                                      -                                          V                DAC                            ⁡                              [                i                ]                                                    ,                              where            ⁢                                                  ⁢                                          V                DAC                            ⁡                              [                i                ]                                              =                      [                          ±                                                ∑                  1                  i                                ⁢                                                                            (                                              1                        2                                            )                                        i                                    ⁢                                      V                    REF                                                                        ]                          ,                            Eq        .                                  ⁢        1            wherein the voltage difference Δ(Vxp−Vxn) can be generalized as the value obtained by subtraction of the synthesized DAC voltage VDAC[i] from the sampled signal Vin, where VDAC[i] is the weighted sum of VREF which is determined by the digital code decision. In the Eq. 1, a reference numeral ‘i’ is an integer number denoting the sequence of the decision of codes. ‘i’ is ‘1’ when the MSB is decided, and ‘i’ is ‘4’ when the LSB is decided in a 4-bit ADC, for example. Since ‘i’ increases as the number of bits of the ADC increases, the time required for conversion linearly increases as the ADC resolution increases.
Above-explained code decision process for the 4-bit SAR ADC is illustrated with a DAC waveform in FIG. 3. In FIG. 3, the conversion process is shown with the sampled input signal Vin and the locus of capacitor DAC level change VDAC[i]. For instance, when Vin is greater than VDAC at a given time, the corresponding bit decision becomes ‘1’; otherwise, the bit decision becomes ‘0’. With this operational principle, a complete digital code ‘10110’ is obtained.
To summarize, the term ‘SAR algorithm’ means a serial process of finding voltage VDAC which is closest to the sampled input voltage Vin by using a DAC, and the input code to the DAC is the digital code corresponding to the analog input value.
A/D conversion speed of SAR ADC is determined by the settling time of the DAC output (VDAC). The reason is that an N-bit SAR ADC needs to operate within a certain error range of ADC resolution (generally, a range of 0.5 LSB or less) at every comparison and therefore sufficient time for accurate settling is required. If the given settling time is not sufficient, VDAC will not reach an ideal level, and consequently, a code decision error occurs. Conventional representative techniques to correct code errors caused by DAC error are disclosed in the following documents:    F. Kuttner, “A 1.2V 10 b 20 MSSample/s Non-Binary Successive Approximation ADC in 0.13 μm CMOS”, ISSCC Dig. Tech. Papers, PP. 176-177, February 2002;    M. Hesener, “A 14 b 40 MS/s Redundant SAR ADC with 480 MHz Clock in 0.13 μm CMOS”, ISSCC Dig. Tec. Papers, pp. 248-249, Feb. 2007; and    Masao HOTTA, “SAR ADC Architecture with Digital Error Correction”, IEEJ International Analog VLSI Workshop, 2006.
The first paper has contributed to the improvement of the speed of a SAR ADC while solving a code error caused by a DAC settling error by using a non-binary redundancy algorithm. According to the first document, however, non-binary decision requires a Read Only Memory (ROM), an arithmetic unit and a multiplexer. Accordingly, the complexity of a digital circuit is increased, and thus a conversion speed is degraded by the logic delay.
The second paper, which uses the non-binary redundancy algorithm, is the upgraded version of the first paper. FIG. 4 is a schematic block diagram of the second paper for the comparison with a conventional one. An additional block 44 of FIG. 4 includes a ROM 44A and a processing unit 44B. The processing unit 44B includes an arithmetic unit, flip-flops, a multiplexer and a decoder.
The third paper improves the performance of SAR-DAC by correcting a code error caused by an incomplete DAC settling error by use of simple digital logic gates. FIG. 5 is a block diagram of the third paper. According to the third paper, as shown in FIG. 5, three-times more hardware devices are required than the conventional SAR ADC. Therefore, the method increases power consumption and chip area.